TELKOMNIKA Telecommunication, Computing, Electronics and Control
Hardware accelerator for anti-aliasing Wu's line algorithm using FPGA

TELKOMNIKA Telecommunication, Computing, Electronics and Control
Hardware accelerator for anti-aliasing Wu's line algorithm using FPGA

Anti-aliasing
HLS
Multi-core
Wu’s algorithm
Zynq702 FPGA

Digital images are suffering from the stair-step effect because they are built
from small pixels. This effect termes aliasing and the method uses to decrease

so-called anti-aliasing. This paper offers a hardware accelerator of an anti-
aliasing algorithm using HLS (high level synthesis) along straight-line

segments or edges. These straight-line segments are smoothed by modifying
the intensity of the pixel. The hardware implementation of two different
architectures which is based on Zynq FPGA are presented in this work. The
first architecture is built from one core while the second architecture is built
from multi-core and uses a parallel technique to speed up the algorithm by
dividing line segments into sub-segments and drawing them after smoothing
instantaneously to formulate the main line. This parallel usage leads to a very
fast execution of Wu's algorithm which is represented one-tenth hardware
runtime for one core only. Also, the optimized resource utilization and power
consumption for different cores have been compared, through single-core
design which utilizes 8% and consumes 1.6 W, while utilized resources using
10 cores are 77% with a power consumption of 2 W.

Basma M. K. Younis, Ahmed Kh. Younis

http://journal.uad.ac.id/index.php/TELKOMNIKA

Dec 4, 2020

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