TELKOMNIKA Telecommunication, Computing, Electronics and Control
A 9.38-bit, 422nW, high linear SAR-ADC for wireless implantable system
Dublin Core
Title
TELKOMNIKA Telecommunication, Computing, Electronics and Control
A 9.38-bit, 422nW, high linear SAR-ADC for wireless implantable system
A 9.38-bit, 422nW, high linear SAR-ADC for wireless implantable system
Subject
ADC
Calibration
Clock booster
DAC
Dummy switch
Sample and hold
Successive approximation
register
Calibration
Clock booster
DAC
Dummy switch
Sample and hold
Successive approximation
register
Description
In wireless implantable systems (WIS) low power consumption and linearity
are the most prominent performance metrics in data acquisition systems.
successive approximation register-analog to digital converter (SAR-ADC) is
used for data processing in WIS. In this research work, a 10-bit low power
high linear SAR-ADC has been designed for WIS. The proposed SAR-ADC
architecture is designed using the sample and hold (S/H) circuit consisting of
a bootstrap circuit with a dummy switch. This SAR-ADC has a dynamic latch
comparator, a split capacitance digital to analog converter (SC-DAC) with
mismatch calibration, and a SAR using D-flipflop. This architecture is
designed in 45 nm CMOS technology. This ADC reduces non-linearity errors
and improve the output voltage swing due to the usage of a clock booster and
dummy switch in the sample and hold. The calculated outcomes of the
proposed SAR ADC display that with on-chip calibration an ENOB of 9.38
(bits), spurious free distortion ratio (SFDR) of 58.621 dB, and ± 0.2 LSB DNL
and ± 0.4LSB INL after calibration.
are the most prominent performance metrics in data acquisition systems.
successive approximation register-analog to digital converter (SAR-ADC) is
used for data processing in WIS. In this research work, a 10-bit low power
high linear SAR-ADC has been designed for WIS. The proposed SAR-ADC
architecture is designed using the sample and hold (S/H) circuit consisting of
a bootstrap circuit with a dummy switch. This SAR-ADC has a dynamic latch
comparator, a split capacitance digital to analog converter (SC-DAC) with
mismatch calibration, and a SAR using D-flipflop. This architecture is
designed in 45 nm CMOS technology. This ADC reduces non-linearity errors
and improve the output voltage swing due to the usage of a clock booster and
dummy switch in the sample and hold. The calculated outcomes of the
proposed SAR ADC display that with on-chip calibration an ENOB of 9.38
(bits), spurious free distortion ratio (SFDR) of 58.621 dB, and ± 0.2 LSB DNL
and ± 0.4LSB INL after calibration.
Creator
Silpa Kesav Velagaleti, Nayanathara K. S., Madhavi B. K.
Source
http://journal.uad.ac.id/index.php/TELKOMNIKA
Date
Oct 10, 2020
Contributor
peri irawan
Format
pdf
Language
english
Type
text
Files
Collection
Citation
Silpa Kesav Velagaleti, Nayanathara K. S., Madhavi B. K., “TELKOMNIKA Telecommunication, Computing, Electronics and Control
A 9.38-bit, 422nW, high linear SAR-ADC for wireless implantable system,” Repository Horizon University Indonesia, accessed March 12, 2025, https://repository.horizon.ac.id/items/show/3732.
A 9.38-bit, 422nW, high linear SAR-ADC for wireless implantable system,” Repository Horizon University Indonesia, accessed March 12, 2025, https://repository.horizon.ac.id/items/show/3732.