TELKOMNIKA Telecommunication Computing Electronics and Control
Simulation-based fault-tolerant multiprocessors system
Dublin Core
Title
TELKOMNIKA Telecommunication Computing Electronics and Control
Simulation-based fault-tolerant multiprocessors system
Simulation-based fault-tolerant multiprocessors system
Subject
Fault-tolerant
Multiprocessor
Pipelined
SimEvents
Stateflow
Multiprocessor
Pipelined
SimEvents
Stateflow
Description
System reliability is an important issue in designing modern multiprocessor
systems. This paper proposes a fault-tolerant, scalable, multiprocessor
system architecture that adopts a pipeline scheme. To verify the performance
of the proposed system, the SimEvent/Stateflow tool of the MATLAB
program was used to simulate the system. The proposed system uses twelve
processors (P), connected in a linear array, to build a ten-stage system with
two backup processors (BP). However, the system can be expanded by
adding more processors to increase pipeline stages and performance, and
more backup processors to increase system reliability. The system can
automatically reorganize itself in the event of a failure of one or two
processors and execution continues without interruption. Each processor
communicates with its neighboring processors through input/output (I/O)
ports which are used as bypass links between the processors. In the event of
a processor failure, the function of the faulty processor is assigned to the
next processor that is free from faults. The fast Fourier transform (FFT)
algorithm is implemented on the simulated circuit to evaluate the
performance of the proposed system. The results showed that the system can
continue to execute even if one or two processors fail without a noticeable
decrease in performance.
systems. This paper proposes a fault-tolerant, scalable, multiprocessor
system architecture that adopts a pipeline scheme. To verify the performance
of the proposed system, the SimEvent/Stateflow tool of the MATLAB
program was used to simulate the system. The proposed system uses twelve
processors (P), connected in a linear array, to build a ten-stage system with
two backup processors (BP). However, the system can be expanded by
adding more processors to increase pipeline stages and performance, and
more backup processors to increase system reliability. The system can
automatically reorganize itself in the event of a failure of one or two
processors and execution continues without interruption. Each processor
communicates with its neighboring processors through input/output (I/O)
ports which are used as bypass links between the processors. In the event of
a processor failure, the function of the faulty processor is assigned to the
next processor that is free from faults. The fast Fourier transform (FFT)
algorithm is implemented on the simulated circuit to evaluate the
performance of the proposed system. The results showed that the system can
continue to execute even if one or two processors fail without a noticeable
decrease in performance.
Creator
Ahmad F. Al-Allaf, Ziyad Khalaf Farej
Source
http://telkomnika.uad.ac.id
Date
Nov 12, 2022
Contributor
peri irawan
Format
pdf
Language
english
Type
text
Files
Collection
Citation
Ahmad F. Al-Allaf, Ziyad Khalaf Farej, “TELKOMNIKA Telecommunication Computing Electronics and Control
Simulation-based fault-tolerant multiprocessors system,” Repository Horizon University Indonesia, accessed April 17, 2025, https://repository.horizon.ac.id/items/show/4514.
Simulation-based fault-tolerant multiprocessors system,” Repository Horizon University Indonesia, accessed April 17, 2025, https://repository.horizon.ac.id/items/show/4514.