TELKOMNIKA Telecommunication Computing Electronics and Control
Implementation of FinFET technology based low power 4×4 Wallace tree multiplier using hybrid full adder
Dublin Core
Title
TELKOMNIKA Telecommunication Computing Electronics and Control
Implementation of FinFET technology based low power 4×4 Wallace tree multiplier using hybrid full adder
Implementation of FinFET technology based low power 4×4 Wallace tree multiplier using hybrid full adder
Subject
Binary to excess -1 convertor
Energy delay product
First zero finding logic
Low-power multiplier
Power delay product
Energy delay product
First zero finding logic
Low-power multiplier
Power delay product
Description
Many systems, including digital signal processors, finite impulse response
(FIR) filters, application-specific integrated circuits, and microprocessors,
use multipliers. The demand for low power multipliers is gradually rising
day by day in the current technological trend. In this study, we describe a
4×4 Wallace multiplier based on a carry select adder (CSA) that uses less
power and has a better power delay product than existing multipliers.
HSPICE tool at 16 nm technology is used to simulate the results.
In comparison to the traditional CSA-based multiplier, which has a power
consumption of 1.7 μW and power delay product (PDP) of 57.3 fJ,
the results demonstrate that the Wallace multiplier design employing CSA
with first zero finding logic (FZF) logic has the lowest power consumption
of 1.4 μW and PDP of 27.5 fJ.
(FIR) filters, application-specific integrated circuits, and microprocessors,
use multipliers. The demand for low power multipliers is gradually rising
day by day in the current technological trend. In this study, we describe a
4×4 Wallace multiplier based on a carry select adder (CSA) that uses less
power and has a better power delay product than existing multipliers.
HSPICE tool at 16 nm technology is used to simulate the results.
In comparison to the traditional CSA-based multiplier, which has a power
consumption of 1.7 μW and power delay product (PDP) of 57.3 fJ,
the results demonstrate that the Wallace multiplier design employing CSA
with first zero finding logic (FZF) logic has the lowest power consumption
of 1.4 μW and PDP of 27.5 fJ.
Creator
Shikha Singh, Yagnesh B. Shukla
Source
http://telkomnika.uad.ac.id
Date
Feb 16, 2023
Contributor
peri irawan
Format
pdf
Language
english
Type
text
Files
Collection
Citation
Shikha Singh, Yagnesh B. Shukla, “TELKOMNIKA Telecommunication Computing Electronics and Control
Implementation of FinFET technology based low power 4×4 Wallace tree multiplier using hybrid full adder,” Repository Horizon University Indonesia, accessed November 21, 2024, https://repository.horizon.ac.id/items/show/4596.
Implementation of FinFET technology based low power 4×4 Wallace tree multiplier using hybrid full adder,” Repository Horizon University Indonesia, accessed November 21, 2024, https://repository.horizon.ac.id/items/show/4596.