TELKOMNIKA Telecommunication, Computing, Electronics and Control
High-speed radix-10 multiplication using partial shifter adder tree-based convertor

TELKOMNIKA Telecommunication, Computing, Electronics and Control
High-speed radix-10 multiplication using partial shifter adder tree-based convertor

ASIC
Binary coded decimal
FPGA
ODDS
Partial shifter adder
Radix-10

A radix-10 multiplication is the foremost frequent operations employed by
several monetary business and user-oriented applications, decimal multiplier
using in state of art digital systems are significantly good but can be upgraded
with time delay and area optimization. This work is proposed a more area and
time delay optimized new design of overloaded decimal digit set (ODDS)
architecture-based radix-10 multiplier for signed numbers. Binary coded
decimal (BCD) to binary followed by binary multiplication and finally binary
to BCD conversion are 3 major modules employed in radix-10 multiplication.
This paperwork presents a replacement technique for binary coded decimal
(BCD) to binary and vice-versa convertors in radix-10 multiplication. A novel
addition tree structure called as partial shifter adder (PSA) tree-based approach
has been developed for BCD to binary conversion, and it is used to add
partially generated products. To meet our major concern i.e. speed, we need
particular high-speed multiplication, hence the proposed PSA based radix-10

multiplier is using vertical cross binary multiplication and concurrent shifter-
based addition method. The design has been tested on 45nm technology-based

Zynq-7 field programmable gate array (FPGA) devices with a 6-input lookup
table (LUTs). A combinational implementation maps quite well into the slice
structure of the Xilinx Zynq-7 families field programmable gate array. The
synthesis results for a Zynq-7 device indicate that our design outperforms in
terms of the area and time delay.

Utsav Kumar Malviya

Nov 11, 2020

PERI IRAWAN

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